AD9278

RECOMMENDED FOR NEW DESIGNS

Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator

Analog Devices AD9278 Product Info

10 February 2026 4

Features

8 CHANNELS OF LNA, VGA, AAF, ADC, AND I/Q DEMODULATOR

Low power: 88 mW per channel, TGC mode, 40 MSPS;
32 mW per channel, CW mode
10 mm × 10 mm, 144-ball CSP-BGA
TGC channel input-referred noise: 1.3 nV/√Hz, max gain
Flexible power-down modes
Fast recovery from low power standby mode: <2 μs
Overload recovery: <10 ns

LOW NOISE PREAMPLIFIER (LNA)

Input-referred noise: 1.25 nV/√Hz, gain = 21.3 dB
Programmable gain: 15.6 dB/17.9 dB/21.3 dB
0.1 dB compression: 1000 mV p-p/750 mV p-p/450 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW): >50 MHz

ANTIALIASING FILTER (AAF)

Programmable second-order LPF from 8 MHz to 18 MHz
Programmable HPF

VARIABLE GAIN AMPLIFIER (VGA)

Attenuator range: −45 dB to 0 dB
Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control

ANALOG-TO-DIGITAL CONVERTER (ADC)

SNR: 70 dB, 12 bits up to 65 MSPS
Serial LVDS (ANSI-644, low power/reduced signal)

CW MODE I/Q DEMODULATOR

Individual programmable phase rotation
Output dynamic range per channel: >158 dBc/√Hz
Output-referred SNR: 153 dBc/√Hz, 1 kHz offset, −3dBFS

The AD9278 is designed for low cost, low power,

Part details & applications

The AD9278 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an anti-aliasing filter (AAF); a 12-bit, 10 MSPS to 65 MSPS analog-to-digital converter (ADC); and an I/Q demodulator with programmable phase rotation.

Each channel features a variable gain range of 45 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 51 dB, and an ADC with a conversion rate of up to 65 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.

The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 1.3 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise of the entire channel is 1.3 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is roughly 88 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator. Each demodulator has independently programmable phase rotation through the SPI with 16 phase settings.

The AD9278 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided.

Powering down individual channels is supported to increase battery life for portable applications. A standby mode option allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable ADC speed power modes.

The ADC contains several features des

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