Texas Instruments SN65LVDS4 Product Info

Parameters

Function	Receiver
Protocols	LVDS
Number of transmitters	0
Number of receivers	1
Supply voltage (V)	1.8, 2.5
Signaling rate (Mbps)	500
Input signal	LVDS
Output signal	LVCMOS, LVTTL
Rating	Catalog
Operating temperature range (°C)	-40 to 85

UQFN (RSE)-10-3 mm² 2 x 1.5

Designed for Signaling Rates⁽¹⁾ up to:
- 500-Mbps Receiver
Operates From a 1.8-V or 2.5-V Core Supply
Available in 1.5-mm × 2-mm UQFN Package
Bus-Terminal ESD Exceeds 2 kV (HBM)
Low-Voltage Differential Signaling With Typical
Output Voltages of 350 mV Into a 100-Ω Load
Propagation Delay Times
- 2.1 ns Typical Receiver
Power Dissipation at 250 MHz
- 40 mW Typical
Requires External Failsafe
Differential Input Voltage Threshold Less Than 50
mV
Can Provide Output Voltage Logic Level (3.3-V
LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based
on External VDD Pin, Thus Eliminating External
LevelTranslation

Designed for Signaling Rates⁽¹⁾ up to:
- 500-Mbps Receiver
Operates From a 1.8-V or 2.5-V Core Supply
Available in 1.5-mm × 2-mm UQFN Package
Bus-Terminal ESD Exceeds 2 kV (HBM)
Low-Voltage Differential Signaling With Typical
Output Voltages of 350 mV Into a 100-Ω Load
Propagation Delay Times
- 2.1 ns Typical Receiver
Power Dissipation at 250 MHz
- 40 mW Typical
Requires External Failsafe
Differential Input Voltage Threshold Less Than 50
mV
Can Provide Output Voltage Logic Level (3.3-V
LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based
on External VDD Pin, Thus Eliminating External
LevelTranslation

The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline UQFN package.