AD9548

RECOMMENDED FOR NEW DESIGNS

Quad/Octal Input Network Clock Generator/Synchronizer

Analog Devices AD9548 Product Info

10 February 2026 6

Features

Supports Stratum2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Auto/manual holdover and reference switchover
4 pairs of reference input pins with each pair configurable as a single differential input or as 2 independent single-ended inputs

Input reference frequencies from 1 Hz to 750 MHz
Reference validation and frequency monitoring (1ppm)
Programmable input reference switchover priority
Please see data sheet for additional features.

Part details & applications

The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry.

The AD9548 operates over an industrial temperature range of −40°C to +85°C.

Applications

Network synchronization
Cleanup of reference clock jitter
GPS 1 pulse per second synchronization
SONET/SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient control
Stratum 3E and Stratum 3 reference clocks
Wireless base stations, controllers
Cable infrastructure
Data communications

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