0
ACTIVE
Number of outputs |
26 |
Core supply voltage (V) |
2.5 |
Output supply voltage (V) |
2.5 |
Operating temperature range (°C) |
0 to 70 |
Rating |
Military |
Output type |
SSTL-18 |
Input type |
SSTL-18 |
TSSOP (DGG)-64-137.7 mm² 17 x 8.1
Widebus is a trademark of Texas Instruments.
This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads.
The SN74SSTVF16859 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
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