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SN55LVDS32-SP
  • SN55LVDS32-SP

SN55LVDS32-SP

ACTIVE

Quad LVDS receiver

Texas Instruments SN55LVDS32-SP Product Info

1 April 2026 0

Parameters

Function

Receiver

Protocols

LVDS

Number of transmitters

0

Number of receivers

4

Supply voltage (V)

3.3

Signaling rate (Mbps)

100

Input signal

LVDS

Output signal

LVTTL

Rating

Space

Operating temperature range (°C)

-55 to 125

Package

CFP (W)-16-69.319 mm² 10.3 x 6.73

Features

  • QML-V Qualified, SMD 5962-97621
  • Operate From a Single 3.3-V Supply
  • Designed for Signaling Rates of up to 100 Mbps
  • Differential Input Thresholds ±100 mV Max
  • Typical Propagation Delay Times of 2.1 ns
  • Power Dissipation 60 mW Typical Per Receiver at Maximum Data Rate
  • Bus-Terminal ESD Protection Exceeds 8 kV
  • Low-Voltage TTL (LVTTL) Logic Input Levels
  • Open-Circuit Fail-Safe
  • Cold Sparing for Space and High Reliability Applications Requiring Redundancy

  • QML-V Qualified, SMD 5962-97621
  • Operate From a Single 3.3-V Supply
  • Designed for Signaling Rates of up to 100 Mbps
  • Differential Input Thresholds ±100 mV Max
  • Typical Propagation Delay Times of 2.1 ns
  • Power Dissipation 60 mW Typical Per Receiver at Maximum Data Rate
  • Bus-Terminal ESD Protection Exceeds 8 kV
  • Low-Voltage TTL (LVTTL) Logic Input Levels
  • Open-Circuit Fail-Safe
  • Cold Sparing for Space and High Reliability Applications Requiring Redundancy

Description

The SN55LVDS32 is a differential line receiver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.

The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media and the noise coupling to the environment.

The SN55LVDS32 is characterized for operation from –55°C to 125°C.

The SN55LVDS32 is a differential line receiver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.

The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media and the noise coupling to the environment.

The SN55LVDS32 is characterized for operation from –55°C to 125°C.

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