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SN74ACT596
  • SN74ACT596
  • SN74ACT596
  • SN74ACT596

SN74ACT596

ACTIVE

4.5V to 5.5V, 8-bit serial-in parallel-out shift register

Texas Instruments SN74ACT596 Product Info

1 April 2026 1

Parameters

Configuration

Serial-in

Bits (#)

8

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Open-drain

Clock frequency (MHz)

92

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

2

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Package

TSSOP (PW)-16-32 mm² 5 x 6.4

Features

  • Operating voltage range of 4.5V to 5.5V
  • TTL-compatible inputs
  • Continuous ±24mA output drive at 5V
  • Supports up to ±75mA output drive at 5Vin short bursts
  • Drives 50Ω transmission lines
  • Fast operation with delay of 11.6ns max
  • Operating voltage range of 4.5V to 5.5V
  • TTL-compatible inputs
  • Continuous ±24mA output drive at 5V
  • Supports up to ±75mA output drive at 5Vin short bursts
  • Drives 50Ω transmission lines
  • Fast operation with delay of 11.6ns max

Description

The SN74ACT596 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the outputs are in a high-impedance state. Internal register data is not impacted by the operation of the OE input.

The SN74ACT596 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the outputs are in a high-impedance state. Internal register data is not impacted by the operation of the OE input.

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