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SN74AHCT165-Q1
  • SN74AHCT165-Q1
  • SN74AHCT165-Q1
  • SN74AHCT165-Q1
  • SN74AHCT165-Q1
  • SN74AHCT165-Q1
  • SN74AHCT165-Q1

SN74AHCT165-Q1

ACTIVE

Automotive 4.5-V to 5.5-V 8-bit parallel-load shift register with TTL-compatible CMOS inputs

Texas Instruments SN74AHCT165-Q1 Product Info

1 April 2026 0

Parameters

Technology family

AHCT

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Package

TSSOP (PW)-16-32 mm² 5 x 6.4

Features

  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN (WBQA) package
  • Operating range 4.5-V to 5.5-V V CC
  • TTL-Compatible inputs
  • Low delay, 7 ns (25 °C, 5 V)
  • Latch-up performance exceeds 250 mA per JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN (WBQA) package
  • Operating range 4.5-V to 5.5-V V CC
  • TTL-Compatible inputs
  • Low delay, 7 ns (25 °C, 5 V)
  • Latch-up performance exceeds 250 mA per JESD 17

Description

The SN74AHCT165-Q1 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear ( SRCLR) input, a serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except QH′ are in the high-impedance state.

The SN74AHCT165-Q1 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear ( SRCLR) input, a serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except QH′ are in the high-impedance state.

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