AD9446

PRODUCTION

16-Bit, 80 MSPS / 100 MSPS A/D Converter

Analog Devices AD9446 Product Info

10 February 2026 5

Features

100 MSPS guaranteed sampling rate (AD9446-100)
83.6 dBFS SNR with 30 MHz input (3.8 V p-p input, 80 MSPS)
82.6 dBFS SNR with 30 MHz input (3.2 V p-p input, 80 MSPS)
89 dBc SFDR with 30 MHz input (3.2 V p-p input, 80 MSPS)
95 dBFS 2-tone SFDR with 9.8 MHz and 10.8 MHz (100 MSPS)
60 fsec rms jitter
Excellent linearity
DNL = ±0.4 LSB typical
INL = ±3.0 LSB typical

2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available
3.3 V and 5 V supply operation

Part details & applications

The AD9446 is a 16-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use. The product operates up to 100 MSPS, providing superior SNR for instrumentation, medical imaging, and radar receivers employing baseband (<100 MHz) IF frequencies.

The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS-compatible (ANSI-644) or CMOS-compatible and include the means to reduce the overall current needed for short trace distances.

Optional features allow users to implement various selectable operating conditions, including data format select and output data mode.

The AD9446 is available in a 100-lead surface-mount plastic package (100-lead TQFP/EP) specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

True 16 bit linearity.
High performance: outstanding SNR performance for baseband IFs in data acquisition, instrumentation, magnetic resonance imaging, and radar receivers.
Ease of use: On-chip reference and high input impedance track-and-hold. An output clock simplifies data capture.
Packaged in a Pb-free, 100-lead TQFP/EP.
Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of clock pulse widths.
OR (out-of-range) outputs indicate when the signal is beyond the selected input range.

APPLICATIONS

MRI receivers
Multi-carrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar, infrared imaging

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