0
ACTIVE
Bits (#) |
1 |
Data rate (max) (Mbps) |
420 |
Topology |
Push-Pull |
Direction control (typ) |
Direction-controlled |
Vin (min) (V) |
1.65 |
Vin (max) (V) |
5.5 |
Vout (min) (V) |
1.65 |
Vout (max) (V) |
5.5 |
Applications |
GPIO |
Features |
Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation |
Prop delay (ns) |
3.9 |
Technology family |
LVC |
Supply current (max) (mA) |
0.004 |
Rating |
Catalog |
Operating temperature range (°C) |
-40 to 85 |
DSBGA (YZP)-6-2.1875 mm² 1.75 x 1.25
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.
The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry is always active on both A and B ports and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
The SN74LVC1T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK
