0
ACTIVE
Sample rate (max) (Msps) |
800 |
Resolution (Bits) |
12 |
Number of input channels |
1 |
Interface type |
JESD204B, JESD204C |
Analog input BW (MHz) |
6000 |
Features |
Ultra High Speed |
Rating |
Catalog |
Peak-to-peak input voltage range (V) |
0.8 |
Power consumption (typ) (mW) |
830 |
Architecture |
Folding Interpolating |
SNR (dB) |
57.6 |
ENOB (Bits) |
9 |
SFDR (dB) |
62 |
Operating temperature range (°C) |
-40 to 85 |
Input buffer |
Yes |
FCCSP (AAV)-144-100 mm² 10 x 10
ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems.
Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
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