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SN74LV6T07-EP
  • SN74LV6T07-EP
  • SN74LV6T07-EP

SN74LV6T07-EP

ACTIVE

Enhanced-product six-bit open-drain fixed-direction level translator

Texas Instruments SN74LV6T07-EP Product Info

1 April 2026 5

Parameters

Bits (#)

6

Data rate (max) (Mbps)

6

Vout (min) (V)

1.65

Vout (max) (V)

5.5

Features

Over-voltage tolerant inputs, Single supply

Technology family

LVxT

Rating

HiRel Enhanced Product

Operating temperature range (°C)

-55 to 125

Package

TSSOP (PW)-14-32 mm² 5 x 6.4

Features

  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
    • Over 6.67Mbps operation, (RPU = 1kΩ,CL = 30pF)
    • Up translation from 1.2V to 5V with 1.8V supply
    • Down translation from 5V to 0.8V or even less with any valid supply
  • Supports standard function pinout
  • Latch-up performance exceeds 250mAper JESD 17
  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
    • Over 6.67Mbps operation, (RPU = 1kΩ,CL = 30pF)
    • Up translation from 1.2V to 5V with 1.8V supply
    • Down translation from 5V to 0.8V or even less with any valid supply
  • Supports standard function pinout
  • Latch-up performance exceeds 250mAper JESD 17

Description

The SN74LV6T07-EP device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

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