Product
0
SN74LV3T99-Q1
  • SN74LV3T99-Q1
  • SN74LV3T99-Q1
  • SN74LV3T99-Q1
  • SN74LV3T99-Q1
  • SN74LV3T99-Q1

SN74LV3T99-Q1

ACTIVE

Automotive three-channel configurable gate with logic-level shifter

Texas Instruments SN74LV3T99-Q1 Product Info

1 April 2026 2

Parameters

Technology family

LVxT

Number of channels

3

Vout (min) (V)

1.65

Vout (max) (V)

5.5

Data rate (max) (Mbps)

80

IOH (max) (mA)

-8

IOL (max) (mA)

8

Supply current (max) (µA)

20

Features

Balanced outputs, Over-voltage tolerant inputs, Voltage translation

Input type

TTL-Compatible CMOS

Output type

3-State

Operating temperature range (°C)

-40 to 125

Package

TSSOP (PW)-20-41.6 mm² 6.5 x 6.4

Features

  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B

  • Available in Wettable Flanks QFN package

  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Up to 150Mbps with 5V or 3.3V VCC
  • Supports standard function pinout
  • Latch-up performance exceeds 100mAper JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B

  • Available in Wettable Flanks QFN package

  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Up to 150Mbps with 5V or 3.3V VCC
  • Supports standard function pinout
  • Latch-up performance exceeds 100mAper JESD 17

Description

The SN74LV3T99-Q1 device contains three independent configurable logic gates with 3-state outputs. Each gate has four inputs and performs the Boolean function Y = (A • /C + B • C) ⊕ D. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer by connecting the inputs A, B, C, and D appropriately.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

Subscribe to Welllinkchips !
Your Name
* Email
Popular Posts
Featured Parts More >
Submit a request
CONTACT US
Company address

WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK

Send Enquiry
SEND e-MAIL
Office hour from 9am to 6pm ,
Monday through Friday, UTC/GMT +8