0
ACTIVE
Configuration |
Parallel-in |
Bits (#) |
8 |
Technology family |
LV-A |
Supply voltage (min) (V) |
2 |
Supply voltage (max) (V) |
5.5 |
Input type |
Standard CMOS |
Output type |
Push-Pull |
Clock frequency (MHz) |
85 |
IOL (max) (mA) |
12 |
IOH (max) (mA) |
-12 |
Supply current (max) (µA) |
20 |
Features |
Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
Operating temperature range (°C) |
-40 to 125 |
Rating |
Catalog |
SOIC (D)-16-59.4 mm² 9.9 x 6
The SN74LV165A device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V VCC operation.
When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The LV165A devices feature a clock-inhibit function and a complemented serial output, Q H.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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