Product
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SN74LV125AT
  • SN74LV125AT
  • SN74LV125AT
  • SN74LV125AT
  • SN74LV125AT
  • SN74LV125AT
  • SN74LV125AT

SN74LV125AT

ACTIVE

4-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Texas Instruments SN74LV125AT Product Info

1 April 2026 0

Parameters

Technology family

LV-AT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

4

IOL (max) (mA)

16

Supply current (max) (µA)

20

IOH (max) (mA)

-16

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Package

SOIC (D)-14-51.9 mm² 8.65 x 6

Features

  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V V CC Operation
  • Typical t pd of 3.8 ns at 5 V
  • Typical V OLP (Output Ground Bounce) < 0.8 V at V CC = 5 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 5 V, T A = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V V CC Operation
  • Typical t pd of 3.8 ns at 5 V
  • Typical V OLP (Output Ground Bounce) < 0.8 V at V CC = 5 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 5 V, T A = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

Description

The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high.

The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high.

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