SOIC (D)-8-29.4 mm² 4.9 x 6

The TLC3555-Q1 is a monolithic timing circuit fabricated using a TI CMOS process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies to 3MHz and even beyond. The TLC3555-Q1 improves upon the existing TLC555-Q1 from both a performance and feature standpoint, with tighter specification tolerances and additional features, such as thermal shutdown and power-on reset.

The trigger, threshold, and reset logic of the TLC3555-Q1 follow the same truth table as the TLC555-Q1. Set the reset pin (RESET) high for typical operation, or set the reset pin low to reset the flip-flop and force the output low. The TLC3555-Q1 features an internal pullup resistor from RESET to VDD, which can reduce passive count and save board area.

As a result of low propagation delay and rapid rise and fall times, the TLC3555-Q1 supports higher-frequency astable operation than previous timers such as the NE555 and TLC555-Q1. At a 15V supply, the TLC3555-Q1 achieves a clean square wave at 3.1MHz in TI’s conventional astable test circuit. When used as an oscillator, with the output and inputs tied together, the TLC3555-Q1 achieves an oscillatory frequency of 7.2MHz. Circuit parasitics dominate the response at high frequencies. In addition to the D package, which is pin-to-pin compatible with the TLC555-Q1, the TLC3555-Q1 is offered in a DDF package that enables concise implementations with reduced parasitics.