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SN74HCS164
  • SN74HCS164
  • SN74HCS164
  • SN74HCS164
  • SN74HCS164
  • SN74HCS164
  • SN74HCS164
  • SN74HCS164
  • SN74HCS164
  • SN74HCS164

SN74HCS164

ACTIVE

8-bit serial-in/parallel-out shift register

Texas Instruments SN74HCS164 Product Info

1 April 2026 1

Parameters

Configuration

Serial-in, Parallel-out

Bits (#)

8

Technology family

HCS

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Schmitt-Trigger

Output type

Push-Pull

Clock frequency (MHz)

62

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

2

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Package

SOIC (D)-14-51.9 mm² 8.65 x 6

Features

  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • Extended ambient temperature range: –40°C to +125°C, TA
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • Extended ambient temperature range: –40°C to +125°C, TA

Description

The SN74HCS164 device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear ( CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals.

The SN74HCS164 device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear ( CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals.

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