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LMK1D1208
  • LMK1D1208
  • LMK1D1208

LMK1D1208

ACTIVE

8-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer

Texas Instruments LMK1D1208 Product Info

1 April 2026 4

Parameters

Number of outputs

8

Additive RMS jitter (typ) (fs)

50

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

Package

VQFN (RHD)-28-25 mm² 5 x 5

Features

  • High-performance LVDS clock buffer family with 2 inputs and 4 (2:4) or 8 (2:8) outputs.
  • Output frequency up to 2GHz.
  • Supply voltage: 1.71V to 3.465V
  • Low additive jitter: < maximum 60fs RMS in 12kHz to 20MHz at 156.25MHz

    • Very low phase noise floor: –164dBc/Hz (typical)

  • Very low propagation delay: < 575ps maximum

  • Output skew: 20ps maximum

  • Universal inputs accept LVDS, LVPECL, LVCMOS, LP-HCSL, HCSL and CML inputs
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available:

    • LMK1D1204: 3mm × 3mm, 16-pin VQFN (RGT)

    • LMK1D1208: 5mm × 5mm, 28-pin VQFN (RHD)

  • High-performance LVDS clock buffer family with 2 inputs and 4 (2:4) or 8 (2:8) outputs.
  • Output frequency up to 2GHz.
  • Supply voltage: 1.71V to 3.465V
  • Low additive jitter: < maximum 60fs RMS in 12kHz to 20MHz at 156.25MHz

    • Very low phase noise floor: –164dBc/Hz (typical)

  • Very low propagation delay: < 575ps maximum

  • Output skew: 20ps maximum

  • Universal inputs accept LVDS, LVPECL, LVCMOS, LP-HCSL, HCSL and CML inputs
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available:

    • LMK1D1204: 3mm × 3mm, 16-pin VQFN (RGT)

    • LMK1D1208: 5mm × 5mm, 28-pin VQFN (RHD)

Description

The LMK1D120x clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 or 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The LMK1D12xx family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML or LVCMOS.

The LMK1D12xx is specifically designed for driving 50Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in Figure 8-6 must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, the pin disables the outputs (logic low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8V or 2.5V or 3.3V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D12xx package variant is shown in the table below:

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