0
ACTIVE
Number of outputs |
8 |
Additive RMS jitter (typ) (fs) |
50 |
Core supply voltage (V) |
1.8, 2.5, 3.3 |
Output supply voltage (V) |
1.8, 2.5, 3.3 |
Output skew (ps) |
20 |
Operating temperature range (°C) |
-40 to 105 |
Rating |
Catalog |
Output type |
LVDS |
Input type |
HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL |
VQFN (RHD)-28-25 mm² 5 x 5
Very low phase noise floor: –164dBc/Hz (typical)
Very low propagation delay: < 575ps maximum
Output skew: 20ps maximum
LMK1D1204: 3mm × 3mm, 16-pin VQFN (RGT)
LMK1D1208: 5mm × 5mm, 28-pin VQFN (RHD)
The LMK1D120x clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 or 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The LMK1D12xx family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML or LVCMOS.
The LMK1D12xx is specifically designed for driving 50Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in Figure 8-6 must be applied to the unused negative input pin.
The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, the pin disables the outputs (logic low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
The device operates in 1.8V or 2.5V or 3.3V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D12xx package variant is shown in the table below:
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