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ADC12D1600QML-SP
  • ADC12D1600QML-SP

ADC12D1600QML-SP

ACTIVE

Radiation-hardness-assured (RHA), 300-krad, ceramic, 12-bit, dual 1.6-GSPS or single 3.2-GSPS ADC

Texas Instruments ADC12D1600QML-SP Product Info

1 April 2026 3

Parameters

Sample rate (max) (Msps)

1600, 3200

Resolution (Bits)

12

Number of input channels

1, 2

Interface type

Parallel LVDS

Analog input BW (MHz)

2400

Features

Ultra High Speed

Rating

Space

Peak-to-peak input voltage range (V)

0.8

Power consumption (typ) (mW)

3880

Architecture

Folding Interpolating

SNR (dB)

58.2

ENOB (Bits)

9.3

SFDR (dB)

67.3

Operating temperature range (°C)

-55 to 125

Input buffer

Yes

Radiation, TID (typ) (krad)

300

Radiation, SEL (MeV·cm2/mg)

120

Package

CCGA (NAA)-376-780.6436 mm² 27.94 x 27.94

Features

  • Total Ionizing Dose (TID) to 300 krad(Si)
  • Single Event Latch-up (SEL) > 120 MeV-cm2/mg
  • Wide Temperature Range –55°C to +125°C
  • Low Power Consumption
  • R/W SPI for Extended Control Mode or Simple Pin Control Mode
  • Interleaved Timing Automatic with Manual Skew Adjust
  • Auto-Sync Function for Multi-Chip Systems
  • Time Stamp Feature to Capture External Trigger
  • Test Patterns at Output for System Debug
  • 1:1 Non-Demuxed or 1:2 or 1:4 Parallel Demuxed LVDS Outputs
  • Single 1.9V Power Supply
  • 376 CPGA Hermetic Package
  • Total Ionizing Dose (TID) to 300 krad(Si)
  • Single Event Latch-up (SEL) > 120 MeV-cm2/mg
  • Wide Temperature Range –55°C to +125°C
  • Low Power Consumption
  • R/W SPI for Extended Control Mode or Simple Pin Control Mode
  • Interleaved Timing Automatic with Manual Skew Adjust
  • Auto-Sync Function for Multi-Chip Systems
  • Time Stamp Feature to Capture External Trigger
  • Test Patterns at Output for System Debug
  • 1:1 Non-Demuxed or 1:2 or 1:4 Parallel Demuxed LVDS Outputs
  • Single 1.9V Power Supply
  • 376 CPGA Hermetic Package

Description

The ADC12D1600QML is a low power, high performance CMOS analog-to-digital converter that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a Low Sampling Power Saving Mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.

The ADC1600QML provides a flexible parallel LVDS interface which has multiple SPI programmable options to facilitate board design and ASIC/FPGA data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and support programmable common mode voltage. The output of each channel is configurable in either 1:1 non-demuxed or 1:2 demuxed modes. If used as a single channel ADC, there is an option for 1:4 demuxing of the output. The product comes in a hermetic 376 CPGA package for harsh environments.

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