0
ACTIVE
Configuration |
Parallel-in, Serial-out |
Bits (#) |
8 |
Technology family |
HC |
Supply voltage (min) (V) |
2 |
Supply voltage (max) (V) |
6 |
Input type |
Standard CMOS |
Output type |
Push-Pull |
Clock frequency (MHz) |
24 |
IOL (max) (mA) |
5.2 |
IOH (max) (mA) |
-5.2 |
Supply current (max) (µA) |
80 |
Features |
Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
Operating temperature range (°C) |
-40 to 125 |
Rating |
Catalog |
PDIP (N)-16-181.42 mm² 19.3 x 9.4
The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
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