0
ACTIVE
Number of channels |
20 |
Technology family |
ALVC |
Supply voltage (min) (V) |
1.65 |
Supply voltage (max) (V) |
3.6 |
Input type |
Standard CMOS |
Output type |
3-State |
Clock frequency (max) (MHz) |
150 |
IOL (max) (mA) |
24 |
IOH (max) (mA) |
-24 |
Supply current (max) (µA) |
40 |
Features |
Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) |
Operating temperature range (°C) |
-40 to 85 |
Rating |
Catalog |
SSOP (DL)-56-190.647 mm² 18.42 x 10.35
Widebus, EPIC are trademarks of Texas Instruments.
This 20-bit flip-flop is designed specifically for 1.65-V to 3.6-V VCC operation.
The 20 flip-flops of the SN74ALVCH16721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored.
A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16721 is characterized for operation from 40°C to 85°C.
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