0
ACTIVE
Supply voltage (min) (V) |
1.65 |
Supply voltage (max) (V) |
3.6 |
Number of channels |
18 |
IOL (max) (mA) |
24 |
IOH (max) (mA) |
-24 |
Input type |
LVTTL |
Output type |
LVTTL |
Features |
Balanced outputs, Bus-hold, Ultra high speed (tpd <5ns) |
Technology family |
ALVC |
Rating |
Catalog |
Operating temperature range (°C) |
-40 to 85 |
SSOP (DL)-56-190.647 mm² 18.42 x 10.35
Widebus, UBT are trademarks of Texas Instruments.
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
Data flow in each direction is controlled by output-enable (OEAB and OEBA) and clock-enable (CLKENBA) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL) input.
Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA input is low. The B-to-A data transfer is synchronized with CLK.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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