0
SN74AHCT164
  • SN74AHCT164
  • SN74AHCT164
  • SN74AHCT164
  • SN74AHCT164
  • SN74AHCT164

SN74AHCT164

ACTIVE

4.5-V to 5.5-V 8-bit, parallel-out serial shift registers

Texas Instruments SN74AHCT164 Product Info

1 April 2026 1

Parameters

Configuration

Serial-in

Bits (#)

8

Technology family

AHCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

IOL (max) (mA)

8

IOH (max) (mA)

-8

Supply current (max) (µA)

40

Features

Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Package

TSSOP (PW)-14-32 mm² 5 x 6.4

Features

  • Operating range 4.5V to 5.5V VCC
  • TTL-Compatible inputs
  • Low delay, 14ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17
  • Operating range 4.5V to 5.5V VCC
  • TTL-Compatible inputs
  • Low delay, 14ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17

Description

The SN74AHCT164 is an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Outputs are directly connected to the internal shift register, resulting in immediate output changes as values are shifted into the register. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

The SN74AHCT164 is an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Outputs are directly connected to the internal shift register, resulting in immediate output changes as values are shifted into the register. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

Subscribe to Welllinkchips !
Your Name
* Email
Submit a request