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SN74ACT595-Q1
  • SN74ACT595-Q1
  • SN74ACT595-Q1
  • SN74ACT595-Q1
  • SN74ACT595-Q1

SN74ACT595-Q1

ACTIVE

Automotive 8-bit shift register with 3-state output register

Texas Instruments SN74ACT595-Q1 Product Info

1 April 2026 0

Parameters

Configuration

Serial-in

Bits (#)

8

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (MHz)

92

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

2

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Package

TSSOP (PW)-16-32 mm² 5 x 6.4

Features

  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package
  • Operating voltage range of 4.5V to 5.5V
  • TTL-compatible inputs
  • Continuous ±24mA output drive at 5V
  • Supports up to ±75mA output drive at 5Vin short bursts
  • Drives 50Ω transmission lines
  • Fast operation with delay of 11.9ns max
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package
  • Operating voltage range of 4.5V to 5.5V
  • TTL-compatible inputs
  • Continuous ±24mA output drive at 5V
  • Supports up to ±75mA output drive at 5Vin short bursts
  • Drives 50Ω transmission lines
  • Fast operation with delay of 11.9ns max

Description

The SN74ACT595-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the register outputs are in a high-impedance state. Internal register data is not impacted by the operation of the OE input.

The SN74ACT595-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the register outputs are in a high-impedance state. Internal register data is not impacted by the operation of the OE input.

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