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SN74LVC2G86
  • SN74LVC2G86
  • SN74LVC2G86
  • SN74LVC2G86

SN74LVC2G86

ACTIVE

2-ch, 2-input, 1.65-V to 5.5-V XOR (exclusive OR) gates

Texas Instruments SN74LVC2G86 Product Info

1 April 2026 1

Parameters

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

2

Inputs per channel

2

IOL (max) (mA)

32

Input type

Standard CMOS

IOH (max) (mA)

-32

Output type

Push-Pull

Features

Over-voltage tolerant Inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Package

DSBGA (YZP)-8-2.8125 mm² 2.25 x 1.25

Features

  • Available in the Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.7 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

  • Available in the Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.7 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Description

This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.

This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.

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