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DLPC6422
  • DLPC6422
  • DLPC6422
  • DLPC6422

DLPC6422

ACTIVE

DLP controller for 0.78in high efficiency pixel (HEP) UV DMD

Texas Instruments DLPC6422 Product Info

1 April 2026 1

Parameters

Component type

Controller

Chipset family

DLPA300

Display resolution (max)

4K UHD (3840x2160)

Operating temperature range (°C)

0 to 55

Rating

Catalog

Package

PBGA (ZPC)-516-See data sheet

Features

  • Digital controller for DLP78TUV (.78 inch 8.3-megapixel) DMD
    • Dual controller Up to 4K at 60Hz
    • Single controller Up to 1080p at 120Hz
    Provides a single 30-bit or dual 60-bit input pixel interface:
    • YUV, YCrCb, RGB data format
    • RGB data format
    • 8, 9, or 10 bits per color
    • Pixel clock up to 320MHz in dual 30-bit mode on a single controller
    • Pixel clock up to 600MHz in dual 30-bit mode on dual controllers
  • High-speed, low-voltage differential signaling (LVDS) DMD interface
  • 150MHz ARM946™ microprocessor
  • Microprocessor peripherals
    • Programmable pulse-width modulation (PWM) and capture timers
    • Three I2C ports, three UART ports, and three SSP ports
    • One USB 1.1 secondary port
  • Image processing
    • Multiple image processing algorithms
    • Frame rate conversion
    • Color coordinate adjustment
    • Programmable color space conversion
    • Programmable degamma and splash
  • Integrated clock generation circuitry
    • Operates on a single 20MHz crystal
    • Integrated spread spectrum clocking
  • External memory support
    • Parallel flash for microprocessor and PWM sequence
  • 516-pin plastic ball grid array package
  • Supports LED and laser hybrid illuminations
  • Digital controller for DLP78TUV (.78 inch 8.3-megapixel) DMD
    • Dual controller Up to 4K at 60Hz
    • Single controller Up to 1080p at 120Hz
    Provides a single 30-bit or dual 60-bit input pixel interface:
    • YUV, YCrCb, RGB data format
    • RGB data format
    • 8, 9, or 10 bits per color
    • Pixel clock up to 320MHz in dual 30-bit mode on a single controller
    • Pixel clock up to 600MHz in dual 30-bit mode on dual controllers
  • High-speed, low-voltage differential signaling (LVDS) DMD interface
  • 150MHz ARM946™ microprocessor
  • Microprocessor peripherals
    • Programmable pulse-width modulation (PWM) and capture timers
    • Three I2C ports, three UART ports, and three SSP ports
    • One USB 1.1 secondary port
  • Image processing
    • Multiple image processing algorithms
    • Frame rate conversion
    • Color coordinate adjustment
    • Programmable color space conversion
    • Programmable degamma and splash
  • Integrated clock generation circuitry
    • Operates on a single 20MHz crystal
    • Integrated spread spectrum clocking
  • External memory support
    • Parallel flash for microprocessor and PWM sequence
  • 516-pin plastic ball grid array package
  • Supports LED and laser hybrid illuminations

Description

The DLPC6422 is a digital light controller for the DLP imaging chipset. The chipset comprises the DLPC6422 light controller, the DLP digital micromirror device (DMD) DLP78TUV, the DLPA100 power management device, and the DLPA300 DMD micromirror driver (refer to the DMD data sheet). This system is a great fit for DLP 3D Print and other imaging applications that require high speed, high resolution, UV wavelength, high light throughput, and a robust system. For reliable operation, the DLPC6422 light controller must always be used with a DLP DMD DLP78TUV and respective DLP power management devices.

The DLPC6422 is a digital light controller for the DLP imaging chipset. The chipset comprises the DLPC6422 light controller, the DLP digital micromirror device (DMD) DLP78TUV, the DLPA100 power management device, and the DLPA300 DMD micromirror driver (refer to the DMD data sheet). This system is a great fit for DLP 3D Print and other imaging applications that require high speed, high resolution, UV wavelength, high light throughput, and a robust system. For reliable operation, the DLPC6422 light controller must always be used with a DLP DMD DLP78TUV and respective DLP power management devices.

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