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LMX1204
  • LMX1204
  • LMX1204

LMX1204

ACTIVE

12.8-GHz RF buffer, multiplier and divider with JESD204B/C SYSREF support and phase synchronization

Texas Instruments LMX1204 Product Info

1 April 2026 0

Parameters

Frequency (max) (MHz)

12800

Frequency (min) (MHz)

300

Features

Integrated multiplier and divider modes, JESD204B/C SYSREF support, Phase synchronization, RF clock distribution, Ultra-low additive jitter

Current consumption (mA)

405

Integrated VCO

No

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Lock time (µs) (typ) (s)

Loop BW dependent

Package

VQFN (RHA)-40-36 mm² 6 x 6

Features

  • 300MHz to 12.8GHz output frequency
  • Ultra-low noise
    • Noise floor of –161dBc/Hz at 6GHz output
    • 1/f Noise of –154dBc/Hz at 6GHz output, 10kHz offset
    • 5fs jitter (12kHz to 20MHz)
    • <30fs additive jitter (DC to fCLK )
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divider that supports ÷1 (buffer mode), ÷2, 3, 4, 5, 6, 7, and 8
    • Shared PLL-based multiplier that supports x1 (filter mode), x2, x3, and x4
  • LOGICLK and corresponding SYSREF outputs
    • On separate divide bank
    • ÷1, 2, 4 pre-divider
    • ÷1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –40ºC to 85ºC operating temperature
  • 300MHz to 12.8GHz output frequency
  • Ultra-low noise
    • Noise floor of –161dBc/Hz at 6GHz output
    • 1/f Noise of –154dBc/Hz at 6GHz output, 10kHz offset
    • 5fs jitter (12kHz to 20MHz)
    • <30fs additive jitter (DC to fCLK )
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divider that supports ÷1 (buffer mode), ÷2, 3, 4, 5, 6, 7, and 8
    • Shared PLL-based multiplier that supports x1 (filter mode), x2, x3, and x4
  • LOGICLK and corresponding SYSREF outputs
    • On separate divide bank
    • ÷1, 2, 4 pre-divider
    • ÷1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –40ºC to 85ºC operating temperature

Description

The high-frequency capability and extremely low jitter of this device, makes a great approach to clock precision, high-frequency data converters without degradation to the signal-to-noise ratio. Each of the four high-frequency clock outputs, and additional LOGICLK output with larger divider range, is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. For data converter clocking applications, having the jitter of the clock be less than the aperture jitter of the data converter is critical. In applications where more than four data converters must be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the high-frequency clocks and SYSREF signals required. With low jitter and noise floor, this device combined with an ultra-low noise reference clock source is an exemplary selection for clocking data converters, especially when sampling above 3GHz.

The high-frequency capability and extremely low jitter of this device, makes a great approach to clock precision, high-frequency data converters without degradation to the signal-to-noise ratio. Each of the four high-frequency clock outputs, and additional LOGICLK output with larger divider range, is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. For data converter clocking applications, having the jitter of the clock be less than the aperture jitter of the data converter is critical. In applications where more than four data converters must be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the high-frequency clocks and SYSREF signals required. With low jitter and noise floor, this device combined with an ultra-low noise reference clock source is an exemplary selection for clocking data converters, especially when sampling above 3GHz.

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