- Ultra-low jitter BAW VCO based Wireless clocks
- 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
- 50fs typical/ 62fs maximum RMS jitter at 245.76MHz
- Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
- Programmable DPLL loop bandwidth from 1mHz to 4kHz
- < 1ppt DCO frequency adjustment step size
- Four differential or single-ended DPLL inputs
- 1Hz (1PPS) to 800MHz input frequency
- Digital holdover and hitless switching
- 14 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formats
- Up to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 12 differential outputs on OUT[13:2]_P/N
- 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
- PCIe Gen 1 to 6 compliant
- I2C, 3-wire SPI, or 4-wire SPI
- –40°C to 85°C operating temperature
- Ultra-low jitter BAW VCO based Wireless clocks
- 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
- 50fs typical/ 62fs maximum RMS jitter at 245.76MHz
- Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
- Programmable DPLL loop bandwidth from 1mHz to 4kHz
- < 1ppt DCO frequency adjustment step size
- Four differential or single-ended DPLL inputs
- 1Hz (1PPS) to 800MHz input frequency
- Digital holdover and hitless switching
- 14 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formats
- Up to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 12 differential outputs on OUT[13:2]_P/N
- 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
- PCIe Gen 1 to 6 compliant
- I2C, 3-wire SPI, or 4-wire SPI
- –40°C to 85°C operating temperature
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ACTIVE
