VQFN (RGC)-64-81 mm² 9 x 9

The LMK5C22212A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The network synchronizer integrates 2 DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input.

APLL1 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology (known as the BAW APLL) and can generate output clocks with 40fs typical / 60fs maximum 12kHz to 20MHz RMS jitter at 491.52MHz, independent of the jitter and frequency of the XO and DPLL reference inputs. APLL2/DPLL2 provides an option for a second frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between inputs upon detecting a switchover event. Zero-Delay Mode (ZDM) and phase cancellation can be enabled to control the phase relationship from input to outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.