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IWR2944
  • IWR2944
  • IWR2944

IWR2944

ACTIVE

Single-chip, 76GHz to 81GHz industrial high-performance radar with integrated DSP, MCU and ethernet

Texas Instruments IWR2944 Product Info

1 April 2026 4

Parameters

Type

IC

Frequency range

76 - 81 GHz

Number of receivers

4

Number of transmitters

4

ADC sampling rate (ksps)

37500

TX power (dBm)

13.5

Arm CPU

Arm Cortex-R5F at 300 MHz

Hardware accelerators

Radar hardware accelerator

Edge AI enabled

Yes

DSP type

C66x DSP 360MHz

Interface type

CSI-2, GPIO, I2C, SPI, LVDS, UART

RAM (kByte)

4096

Operating temperature range (°C)

-40 to 125

TI functional safety category

Functional Safety-Compliant

Security

Cryptographic acceleration, Secure storage

Rating

Catalog

Package

FCCSP (ALT)-266-1728 mm² 12 x 144

Features

  • FMCW transceiver
    • Integrated PLL, transmitter, receiver, baseband and ADC
    • 76 to 81GHz coverage with over 4.5GHz continuous bandwidth
    • 4 receive and 4 transmit channels for PCB interface to antennas
    • Per transmit phase shifter
    • Ultra-accurate chirp engine based on fractional-N PLL
    • TX power
      • 13.5dBm
    • RX noise figure
      • 12dBm
    • Phase noise at 1MHz
      • -96dBc/Hz (76 to 77GHz)
      • -95dBc/Hz (76 to 81GHz)

  • Built-in calibration and self-test

    • Built in firmware (ROM)
    • Self-calibrating system across process and temperature
  • Processing elements
    • Arm Cortex-R5F core (supports lock step operation) @300MHz
    • TI digital signal processor C66x @360MHz
    • TI radar hardware accelerator (HWA2.1) for operations like FFT, log magnitude, and memory compression
    • Multiple EDMA instances for data movement
  • Host interface
    • 2x CAN-FD
    • 10/100Mbps RGMII/RMII/MII Ethernet
  • Supports a serial flash memory interface (loading user application from QSPI flash memory)
  • Other interfaces available to user application
    • Up to 9 ADC channels
    • 2 SPIs
    • 4 UARTs
    • I2C
    • GPIOs
    • 3 EPWMs
    • 4-lane Aurora LVDS interface for raw ADC data and debug instrumentation
    • CSI2 Rx interface to enable playback of the captured data
  • On-Chip RAM
    • 4MBytes of ‘On Chip’ RAM
    • Memory space split between DSP, MCU, and shared L3
  • Device security (on select part numbers)
    • Programmable embedded hardware security module (HSM)
    • Secure authenticated and encrypted boot support
    • Customer programmable root keys, symmetric keys (256 bit), asymmetric keys (up to RSA-4K or ECC-512) with key revocation capability
    • Cryptographic hardware accelerators: PKA with ECC, AES (up to 256 bit), SHA (up to 512 bit), TRNG/DRBG
  • Functional safety compliant targeted
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Hardware integrity up to SIL-2 targeted
  • Advanced features
    • Embedded self-monitoring with no external processor involvement
    • Embedded interference detection capability
  • Power management
    • On-die LDO network for enhanced PSRR
    • LVCMOS IO supports dual voltage 3.3V and 1.8V
  • Clock source
    • 40MHz crystal with internal oscillator
    • Supports external oscillator at 40MHz
    • Supports externally driven clock (square or sine wave) at 40MHz
  • Effective Power Management
    • Recommended LP87745 Power Management ICs (PMIC)
      • Companion PMIC specially designed to meet device power supply requirements
      • Flexible mapping and factory programmed configurations to support different use cases
  • Cost-reduced hardware design
    • 0.65mm pitch, 12mm × 12mm flip chip BGA package for easy assembly and low-cost PCB design
    • Small solution size
  • Supports wide temperature operating range
    • Operating junction temperature range: –40°C to 125°C
  • FMCW transceiver
    • Integrated PLL, transmitter, receiver, baseband and ADC
    • 76 to 81GHz coverage with over 4.5GHz continuous bandwidth
    • 4 receive and 4 transmit channels for PCB interface to antennas
    • Per transmit phase shifter
    • Ultra-accurate chirp engine based on fractional-N PLL
    • TX power
      • 13.5dBm
    • RX noise figure
      • 12dBm
    • Phase noise at 1MHz
      • -96dBc/Hz (76 to 77GHz)
      • -95dBc/Hz (76 to 81GHz)

  • Built-in calibration and self-test

    • Built in firmware (ROM)
    • Self-calibrating system across process and temperature
  • Processing elements
    • Arm Cortex-R5F core (supports lock step operation) @300MHz
    • TI digital signal processor C66x @360MHz
    • TI radar hardware accelerator (HWA2.1) for operations like FFT, log magnitude, and memory compression
    • Multiple EDMA instances for data movement
  • Host interface
    • 2x CAN-FD
    • 10/100Mbps RGMII/RMII/MII Ethernet
  • Supports a serial flash memory interface (loading user application from QSPI flash memory)
  • Other interfaces available to user application
    • Up to 9 ADC channels
    • 2 SPIs
    • 4 UARTs
    • I2C
    • GPIOs
    • 3 EPWMs
    • 4-lane Aurora LVDS interface for raw ADC data and debug instrumentation
    • CSI2 Rx interface to enable playback of the captured data
  • On-Chip RAM
    • 4MBytes of ‘On Chip’ RAM
    • Memory space split between DSP, MCU, and shared L3
  • Device security (on select part numbers)
    • Programmable embedded hardware security module (HSM)
    • Secure authenticated and encrypted boot support
    • Customer programmable root keys, symmetric keys (256 bit), asymmetric keys (up to RSA-4K or ECC-512) with key revocation capability
    • Cryptographic hardware accelerators: PKA with ECC, AES (up to 256 bit), SHA (up to 512 bit), TRNG/DRBG
  • Functional safety compliant targeted
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Hardware integrity up to SIL-2 targeted
  • Advanced features
    • Embedded self-monitoring with no external processor involvement
    • Embedded interference detection capability
  • Power management
    • On-die LDO network for enhanced PSRR
    • LVCMOS IO supports dual voltage 3.3V and 1.8V
  • Clock source
    • 40MHz crystal with internal oscillator
    • Supports external oscillator at 40MHz
    • Supports externally driven clock (square or sine wave) at 40MHz
  • Effective Power Management
    • Recommended LP87745 Power Management ICs (PMIC)
      • Companion PMIC specially designed to meet device power supply requirements
      • Flexible mapping and factory programmed configurations to support different use cases
  • Cost-reduced hardware design
    • 0.65mm pitch, 12mm × 12mm flip chip BGA package for easy assembly and low-cost PCB design
    • Small solution size
  • Supports wide temperature operating range
    • Operating junction temperature range: –40°C to 125°C

Description

The IWR2944 is a single-chip mmWave sensor composed of a FMCW transceiver, capable of operation in the 76 to 81GHz band, radar data processing elements, and peripherals for in-vehicle networking. The IWR2944 is built with TI’s low-power 45nm RFCMOS process and enables unprecedented levels of integration in a small form factor and minimal BOM. The IWR2944 is a device for low-power, self-monitored, ultra-accurate radar systems in the industrial space.

TI’s low-power 45nm RFCMOS process enables a monolithic implementation of a 4 TX, 4 RX system with integrated PLL, VCO, mixer, and baseband ADC. Integrated in the DSP subsystem (DSS), is TI’s high-performance C66x DSP for radar signal processing. The device includes a Radio Processor Subsystem (RSS), which is responsible for radar front-end configuration, control, and calibration. Within the Main Subsystem (MSS), the device implements a user-programmable Arm Cortex-R5F processor allowing for custom control and industrial interface applications. The hardware accelerator block (HWA 2.1) supplements the DSS and MSS by offloading common radar processing such as FFT, constant false alarm rate (CFAR), scaling, and compression. This saves MIPS on the DSS and MSS, opening up resources for custom applications and higher-level algorithms.

A Hardware Security Module (HSM) is also provisioned in the device (available for only secure part variants). The HSM consists of a programmable Arm Cortex-M4 core and the necessary infrastructure to provide a secure zone of operation within the device.

Simple programming model changes can enable a wide variety of sensor implementation (Short, Mid, Long) with the possibility of dynamic reconfiguration for implementing a multimode sensor.

Additionally, the IWR2944 is provided as a complete platform solution including TI hardware and software reference designs, software drivers, sample configurations, API guides, and user documentation.

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