Texas Instruments DM505 Product Info

Parameters

CPU	32-bit
Display type	Display subsystem
Operating system	Android, Linux, RTOS, TI RTOS
Rating	Catalog
Operating temperature range (°C)	-40 to 125

Package

FCBGA (ABF)-367-225 mm² 15 x 15

Features

Architecture Designed for Vision Analytics Applications
Video and Image Processing Support
- Full-HD Video (1920 × 1080p, 60 fps)
- Video Input and Video Output
Up to 2 C66x Floating-Point VLIW DSP
- Fully Object-Code Compatible With C67x and C64x+
- Up to Thirty-two 16 × 16-Bit Fixed-Point Multiplies per Cycle
Up to 512kB of On-Chip L3 RAM
Level 3 (L3) and Level 4 (L4) Interconnects
Memory Interface (EMIF) Module
- Supports DDR3/DDR3L up to DDR-1066
- Supports DDR2 up to DDR-800
- Supports LPDDR2 up to DDR-667
- Up to 2GB Supported
Dual Arm^® Cortex^®-M4 Image Processor (IPU)
Vision AccelerationPac
- Embedded Vision Engine (EVE)
Display Subsystem
- Display Controller With DMA Engine
- CVIDEO / SD-DAC TV Analog Composite Output
Video Input Port (VIP) Module
- Support for up to 4 Multiplexed Input Ports
On-chip Temperature Sensor That is Capable of Generating Temperature Alerts
General-Purpose Memory Controller (GPMC)
Enhanced Direct Memory Access (EDMA) Controller
3-Port (2 External) Gigabit Ethernet (GMAC) Switch
Controller Area Network (DCAN) Module
- CAN 2.0B Protocol
Modular Controller Area Network (MCAN) Module
- CAN 2.0B Protocol
Eight 32-Bit General-Purpose Timers
Three Configurable UART Modules
Four Multichannel Serial Peripheral Interfaces (McSPI)
Quad SPI Interface
Two Inter-Integrated Circuit (I²C) Ports
Three Multichannel Audio Serial Ports (McASP) Modules
MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO)
Up to 126 General-Purpose I/O (GPIO) Pins
Power, Reset, and Clock Management
On-Chip Debug With CTools Technology
Automotive AEC-Q100 Qualified
15 × 15mm, 0.65-mm Pitch, 367-Pin PBGA (ABF)
8-Channel 10-bit ADC
MIPI CSI-2 Camera Serial Interface
PWMSS
Full HW Image Pipe: DPC, CFA, 3D-NF, RGB-YUV
- WDR, HW LDC and Perspective

Architecture Designed for Vision Analytics Applications
Video and Image Processing Support
- Full-HD Video (1920 × 1080p, 60 fps)
- Video Input and Video Output
Up to 2 C66x Floating-Point VLIW DSP
- Fully Object-Code Compatible With C67x and C64x+
- Up to Thirty-two 16 × 16-Bit Fixed-Point Multiplies per Cycle
Up to 512kB of On-Chip L3 RAM
Level 3 (L3) and Level 4 (L4) Interconnects
Memory Interface (EMIF) Module
- Supports DDR3/DDR3L up to DDR-1066
- Supports DDR2 up to DDR-800
- Supports LPDDR2 up to DDR-667
- Up to 2GB Supported
Dual Arm^® Cortex^®-M4 Image Processor (IPU)
Vision AccelerationPac
- Embedded Vision Engine (EVE)
Display Subsystem
- Display Controller With DMA Engine
- CVIDEO / SD-DAC TV Analog Composite Output
Video Input Port (VIP) Module
- Support for up to 4 Multiplexed Input Ports
On-chip Temperature Sensor That is Capable of Generating Temperature Alerts
General-Purpose Memory Controller (GPMC)
Enhanced Direct Memory Access (EDMA) Controller
3-Port (2 External) Gigabit Ethernet (GMAC) Switch
Controller Area Network (DCAN) Module
- CAN 2.0B Protocol
Modular Controller Area Network (MCAN) Module
- CAN 2.0B Protocol
Eight 32-Bit General-Purpose Timers
Three Configurable UART Modules
Four Multichannel Serial Peripheral Interfaces (McSPI)
Quad SPI Interface
Two Inter-Integrated Circuit (I²C) Ports
Three Multichannel Audio Serial Ports (McASP) Modules
MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO)
Up to 126 General-Purpose I/O (GPIO) Pins
Power, Reset, and Clock Management
On-Chip Debug With CTools Technology
Automotive AEC-Q100 Qualified
15 × 15mm, 0.65-mm Pitch, 367-Pin PBGA (ABF)
8-Channel 10-bit ADC
MIPI CSI-2 Camera Serial Interface
PWMSS
Full HW Image Pipe: DPC, CFA, 3D-NF, RGB-YUV
- WDR, HW LDC and Perspective

Description

The DM505 is a highly optimized device for Vision Analytics and Machine Vision processing in Industrial products such as drones, robots, forklifts, railroad and agriculture equipment. The Processor enables sophisticated embedded vision processing integrating an optimal mix of real time performance, low power, small form factor and camera processing for systems to interact in more intelligent, useful ways with the physical world and the people in it.

The DM505 incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac (EVE), and dual-Cortex-M4 processors. The device allows low power designs to meet demanding embedded system budgets without sacrificing real-time processing performance to enable small form factor designs. The DM505 also integrates a host of peripherals including interfaces for multi-camera input (both parallel and serial), display outputs, audio and serial I/O, CAN and GigB Ethernet AVB.

TI provides application specific hardware and software through our Design Network Partners and a complete set of development tools for the Arm, and DSP, including C compilers with TI RTOS to accelerate time to market.