Product
0
SN74LV573A
  • SN74LV573A
  • SN74LV573A
  • SN74LV573A
  • SN74LV573A
  • SN74LV573A
  • SN74LV573A
  • SN74LV573A
  • SN74LV573A
  • SN74LV573A

SN74LV573A

ACTIVE

Octal Transparent D-Type Latches With 3-State Outputs

Texas Instruments SN74LV573A Product Info

1 April 2026 0

Parameters

Number of channels

8

Technology family

LV-A

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

70

IOL (max) (mA)

16

IOH (max) (mA)

-16

Supply current (max) (µA)

20

Features

Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Package

SOIC (DW)-20-131.84 mm² 12.8 x 10.3

Features

  • V CC operation of 2 V to 5.5 V
  • Max t pd of 8 ns at 5 V
  • Typical V OLP (Output Ground Bounce) latch-up performance exceeds 250 mA per <0.8 V at V CC = 3.3 V , T A = 25°C
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Support mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • V CC operation of 2 V to 5.5 V
  • Max t pd of 8 ns at 5 V
  • Typical V OLP (Output Ground Bounce) latch-up performance exceeds 250 mA per <0.8 V at V CC = 3.3 V , T A = 25°C
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Support mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17

Description

SN74LV573A:Octal Transparent D-Type Latches With 3-State Outputs.Package:SOIC (DW)-20-131.84 mm² 12.8 x 10.3

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