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ADS42JB69
  • ADS42JB69
  • ADS42JB69

ADS42JB69

ACTIVE

Dual-Channel, 16-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

Texas Instruments ADS42JB69 Product Info

1 April 2026 0

Parameters

Sample rate (max) (Msps)

250

Resolution (Bits)

16

Number of input channels

2

Interface type

JESD204B

Analog input BW (MHz)

900

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2.5

Power consumption (typ) (mW)

1700

Architecture

Pipeline

SNR (dB)

75.9

ENOB (Bits)

12.1

SFDR (dB)

95

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Package

VQFN (RGC)-64-81 mm² 9 x 9

Features

  • Dual-Channel ADCs
  • 14- and 16-Bit Resolution
  • Maximum Clock Rate: 250 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two and Four Lanes Support
  • Analog Input Buffer with High-Impedance Input
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm VQFN-64
  • Power Dissipation: 850 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 73.3 dBFS
      • SFDR: 93 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.7 dBFS
      • SFDR: 89 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3
  • Dual-Channel ADCs
  • 14- and 16-Bit Resolution
  • Maximum Clock Rate: 250 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two and Four Lanes Support
  • Analog Input Buffer with High-Impedance Input
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm VQFN-64
  • Power Dissipation: 850 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 73.3 dBFS
      • SFDR: 93 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.7 dBFS
      • SFDR: 89 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3

Description

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

For all available packages, see the orderable addendum at the end of the datasheet.

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

For all available packages, see the orderable addendum at the end of the datasheet.

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