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ADRV9008-1
  • ADRV9008-1

ADRV9008-1

RECOMMENDED FOR NEW DESIGNS

Integrated Dual RF Receiver

Analog Devices ADRV9008-1 Product Info

10 February 2026 4

Features

  • Dual receivers
  • Maximum Receiver BW: 200 MHz
  • Fully integrated, fractional-N, RF synthesizers
  • Fully integrated clock synthesizer
  • Multichip phase synchronization for RF LO and baseband clocks
  • JESD204B datapath interface
  • Tuneable range: 75 MHz to 6000 MHz

Part details & applications

The receive path consists of two independent, wide bandwidth (BW), direct conversion receivers with state-of-the-art dynamic range. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. RF front-end control and several auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) for the power amplifier (PA) are also integrated.

In addition to automatic gain control (AGC), the ADRV9008-1 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.

The received signals are digitized with a set of four high dynamic range, continuous time, sigma-delta (Σ-Δ) ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing relaxes the requirements of the RF filters compared to traditional intermediate frequency (IF) receivers.

The fully integrated phase-locked loop (PLL) provides high per-formance, low power, fractional-N, RF synthesis for the receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multi-chip synchronization mechanism synchronizes the phase of the RF local oscillato

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