Analog Devices AD9958 Product Info

• 2 synchronized DDS channels at 500 MSPS
• Independent frequency/phase/amplitude control between channels
• Matched latencies for frequency/phase/amplitude changes
• Excellent channel-to-channel isolation (>72 dB)
• Linear frequency/phase/amplitude sweeping capability
• Up to 16 levels of frequency/phase/amplitude modulation (pin-selectable)
• 2 integrated 10-bit digital-to-analog converters (DACs)
• Individually programmable DAC full-scale currents
• 0.12 Hz or better frequency tuning resolution
• 14-bit phase offset resolution
• 10-bit output amplitude scaling resolution
• Serial I/O port interface (SPI) with 800 Mbps data throughput
• Software-/hardware-controlled power-down
• Dual supply operation (1.8 V DDS core/3.3 V serial I/O)
• Multiple device synchronization
• Selectable 4× to 20× REFCLK multiplier (PLL)
• Selectable REFCLK crystal oscillator
• 56-lead LFCSP

The AD9958 consists of two DDS cores that provide independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such as filtering, amplification, or PCB layout related mismatches. Because both channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported.

The AD9958 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9958 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.

The AD9958 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPIcompatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices, Inc., DDS products. Flexibility is provided by four data pins (SDIO_0 / SDIO_1 / SDIO_2 / SDIO_3) that allow four programmable modes of serial I/O operation.

The AD9958 uses advanced DDS technology that provides low power dissipation with high performance. The device incorporates two integrated, high speed 10-bit DACs with excellent wideband and narrow-band SFDR. Each channel has a dedicated 32-bit frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier.

The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable different full-scale currents for each channel.

The DDS acts as a high resolution frequency divider with the REFCLK as the input and the DAC providing the output. The REFCLK input source is common to both channels and can be driven directly or used in combination with an integrated REFCLK multipli