AD4058

RECOMMENDED FOR NEW DESIGNS

Compact, Low Power, 16-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC

Analog Devices AD4058 Product Info

10 February 2026 5

Features

Small footprint, big performance

INL: ±0.5 LSB maximum
SNR: 86.1 dB with V_REF = 3.3 V
1.35 nJ per conversion
1.35 mW/0.68 mW at 1 MSPS/500 kSPS in sample mode
370 μW/112 μW at 1 MSPS/300 kSPS in autonomous modes
4.1 μW standby power

Versatile signal conditioning integration

Easy Drive features enable small, low-power AFE designs
Compatible with differential and single-ended signal chains
Wide common-mode input range

Minimizes digital host activity and power dissipation

Autonomous sampling with window comparator and interrupt generation
Averaging filter with continuous and burst sampling options
Power cycling synchronization for companion devices

4-wire SPI compatible with 1.8 V to 3.3 V logic
2.0 mm × 2.6 mm LFCSP and 1.7 mm × 2.0 mm WLCSP
Wide operating temperature range: −40°C to +125°C

Part details & applications

The AD4052/AD4058 are versatile, 16-bit, successive approximation register (SAR) analog-to-digital converter (ADC) that enables low-power, high-density data acquisition solutions without sacrificing precision. This ADC offers a unique balance of performance and power efficiency, plus innovative features for seamlessly switching between high-resolution and low-power modes tailored to the immediate needs of the system. The AD4052/AD4058 are ideal for battery-powered, compact data acquisition and edge sensing applications.

The Easy Drive features enable highly efficient analog front end (AFE) designs. The small sampling capacitors (3.4 pF) maximize input impedance, thus reducing the dependence on high-bandwidth, power-hungry amplifiers typically required by SAR ADCs. The wide input common-mode range grants inherent support for both differential and single-ended signals.

The AD4052/AD4058 support microcontrollers with power-down modes and interrupt-driven firmware. The autonomous modes enable out-of- range event detection while the digital host sleeps. The averaging modes deliver on-demand, high-resolution measurements while offloading computations from the host processor. The self-timed device enable signal (DEV_EN) synchronizes AFE device power cycling to the ADC sampling instant, optimizing system power consumption while minimizing power-up settling error artifacts. The AD4052/AD4058 also supports power cycling the voltage reference and using the supply as the ADC reference voltage (V_REF) for additional power savings.

Device configuration and ADC data readback are supported via a robust, 4-wire serial peripheral interface (SPI) with cyclic redundancy check (CRC) supported for all data transfers. The AD4052/AD4058 are available in compact LFCSP and WLCSP packages and operates across a wide temperature range, making it ideal for a diverse set of applications.

Applications

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