0
ADRV9026
  • ADRV9026
  • ADRV9026

ADRV9026

RECOMMENDED FOR NEW DESIGNS

Integrated, Quad RF Transceiver with Observation Path

Analog Devices ADRV9026 Product Info

10 February 2026 6

Features

  • 4 differential transmitters
  • 4 differential receivers
  • 2 observation receivers with 2 inputs each
  • Center frequency: 75 MHz to 6000 MHz
  • Maximum receiver bandwidth: 200 MHz
  • Maximum transmitter large signal bandwidth: 200 MHz
  • Maximum transmitter synthesis bandwidth: 450 MHz
  • Maximum observation receiver bandwidth: 450 MHz
  • Fully integrated independent fractional-N radio frequency synthesizers
  • Fully integrated clock synthesizer
  • Multichip phase synchronization for all local oscillators and baseband clocks
  • Support for TDD and FDD applications
  • 24.33 Gbps JESD204B/JESD204C digital interface

Part details & applications

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.

The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.

The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated.

To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.

A multichip

Subscribe to Welllinkchips !
Your Name
* Email
Submit a request