Product
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TMS320F28052
  • TMS320F28052
  • TMS320F28052

TMS320F28052

ACTIVE

C2000™ 32-bit MCU with 60 MHz, 64 KB flash, PGAs, 3.75 MSPS ADC

Texas Instruments TMS320F28052 Product Info

1 April 2026 0

Parameters

CPU

1 C28

Frequency (MHz)

60

Flash memory (kByte)

64

RAM (kByte)

20

ADC type

12-bit

Total processing (MIPS)

60

Features

32-bit CPU timers, PGA, Single zone code security, Watchdog timer

UART

3

CAN (#)

1

Sigma-delta filter

0

PWM (Ch)

14

TI functional safety category

Functional Safety Quality-Managed

Number of ADC channels

16

Direct memory access (Ch)

0

SPI

1

QEP

1

USB

No

Hardware accelerators

CPU only

Edge AI enabled

Yes

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Communication interface

CAN, I2C, SPI, UART

Operating system

FreeRTOS

Nonvolatile memory (kByte)

256

Number of GPIOs

42

Number of I2Cs

1

Security

Secure storage

Package

LQFP (PN)-80-196 mm² 14 x 14

Features

  • High-efficiency 32-bit CPU (TMS320C28x)
    • 60 MHz (16.67-ns cycle time)
    • 16 × 16 and 32 × 32 Multiply and Accumulate (MAC) operations
    • 16 × 16 dual MAC
    • Harvard bus architecture
    • Atomic operations
    • Fast interrupt response and processing
    • Unified memory programming model
    • Code-efficient (in C/C++ and Assembly)
  • Programmable Control Law Accelerator (CLA)
    • 32-bit floating-point math accelerator
    • Executes code independently of the main CPU
  • Dual-zone security module
  • Endianness: Little endian
  • Low device and system cost:
    • Single 3.3-V supply
    • No power sequencing requirement
    • Integrated power-on reset and brownout reset
    • Low power
    • No analog support pins
  • Clocking:
    • Two internal zero-pin oscillators
    • On-chip crystal oscillator and external clock input
    • Watchdog timer module
    • Missing clock detection circuitry
  • Up to 42 individually programmable, multiplexed General-Purpose Input/Output (GPIO) pins with input filtering
  • JTAG boundary scan support
    • IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
  • Peripheral Interrupt Expansion (PIE) block that supports all peripheral interrupts
  • Three 32-bit CPU timers
  • Independent 16-bit timer in each ePWM module
  • On-chip memory
    • Flash, SARAM, Message RAM, OTP, CLA Data ROM, Boot ROM, Secure ROM available
  • 128-bit security key and lock
    • Protects secure memory blocks
    • Prevents firmware reverse-engineering
  • Serial port peripherals
    • Three Serial Communications Interface (SCI) (Universal Asynchronous Receiver/Transmitter [UART]) modules
    • One Serial Peripheral Interface (SPI) module
    • One Inter-Integrated-Circuit (I2C) bus
    • One Enhanced Controller Area Network (eCAN) bus
  • Enhanced control peripherals
    • Enhanced Pulse Width Modulator (ePWM)
    • Enhanced Capture (eCAP) module
    • Enhanced Quadrature Encoder Pulse (eQEP) module
  • Analog peripherals
    • One 12-bit Analog-to-Digital Converter (ADC)
    • One on-chip temperature sensor for oscillator compensation
    • Up to seven comparators with up to three integrated Digital-to-Analog Converters (DACs)
    • One buffered reference DAC
    • Up to four Programmable Gain Amplifiers (PGAs)
    • Up to four digital filters
  • Advanced debug features
    • Analysis and breakpoint functions
    • Real-time debug through hardware
  • 80-pin PN Low-Profile Quad Flatpack (LQFP)
  • Temperature options
    • T: –40°C to 105°C
    • S: –40°C to 125°C
    • Q: –40°C to 125°C (AEC Q100 qualification for automotive applications)
  • High-efficiency 32-bit CPU (TMS320C28x)
    • 60 MHz (16.67-ns cycle time)
    • 16 × 16 and 32 × 32 Multiply and Accumulate (MAC) operations
    • 16 × 16 dual MAC
    • Harvard bus architecture
    • Atomic operations
    • Fast interrupt response and processing
    • Unified memory programming model
    • Code-efficient (in C/C++ and Assembly)
  • Programmable Control Law Accelerator (CLA)
    • 32-bit floating-point math accelerator
    • Executes code independently of the main CPU
  • Dual-zone security module
  • Endianness: Little endian
  • Low device and system cost:
    • Single 3.3-V supply
    • No power sequencing requirement
    • Integrated power-on reset and brownout reset
    • Low power
    • No analog support pins
  • Clocking:
    • Two internal zero-pin oscillators
    • On-chip crystal oscillator and external clock input
    • Watchdog timer module
    • Missing clock detection circuitry
  • Up to 42 individually programmable, multiplexed General-Purpose Input/Output (GPIO) pins with input filtering
  • JTAG boundary scan support
    • IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
  • Peripheral Interrupt Expansion (PIE) block that supports all peripheral interrupts
  • Three 32-bit CPU timers
  • Independent 16-bit timer in each ePWM module
  • On-chip memory
    • Flash, SARAM, Message RAM, OTP, CLA Data ROM, Boot ROM, Secure ROM available
  • 128-bit security key and lock
    • Protects secure memory blocks
    • Prevents firmware reverse-engineering
  • Serial port peripherals
    • Three Serial Communications Interface (SCI) (Universal Asynchronous Receiver/Transmitter [UART]) modules
    • One Serial Peripheral Interface (SPI) module
    • One Inter-Integrated-Circuit (I2C) bus
    • One Enhanced Controller Area Network (eCAN) bus
  • Enhanced control peripherals
    • Enhanced Pulse Width Modulator (ePWM)
    • Enhanced Capture (eCAP) module
    • Enhanced Quadrature Encoder Pulse (eQEP) module
  • Analog peripherals
    • One 12-bit Analog-to-Digital Converter (ADC)
    • One on-chip temperature sensor for oscillator compensation
    • Up to seven comparators with up to three integrated Digital-to-Analog Converters (DACs)
    • One buffered reference DAC
    • Up to four Programmable Gain Amplifiers (PGAs)
    • Up to four digital filters
  • Advanced debug features
    • Analysis and breakpoint functions
    • Real-time debug through hardware
  • 80-pin PN Low-Profile Quad Flatpack (LQFP)
  • Temperature options
    • T: –40°C to 105°C
    • S: –40°C to 125°C
    • Q: –40°C to 125°C (AEC Q100 qualification for automotive applications)

Description

C2000™ real-time control MCUs are optimized for processing, sensing, and actuation to improve closed-loop performance in real-time control applications such as industrial motor drives; solar inverters and digital power; electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes the Premium performance MCUs and the Entry performance MCUs.

The F2805x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration.

An internal voltage regulator allows for single-rail operation. Analog comparators with internal 6-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency.

The Analog Front End (AFE) contains up to seven comparators with up to three integrated DACs, one VREFOUT-buffered DAC, up to four PGAs, and up to four digital filters. The PGAs can amplify the input signal in three discrete gain modes. The actual number of AFE peripherals will depend upon the TMS320F2805x device number. See Device Comparison for more details.

To learn more about the C2000 MCUs, visit the C2000™ real-time control MCUs page.

C2000™ real-time control MCUs are optimized for processing, sensing, and actuation to improve closed-loop performance in real-time control applications such as industrial motor drives; solar inverters and digital power; electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes the Premium performance MCUs and the Entry performance MCUs.

The F2805x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration.

An internal voltage regulator allows for single-rail operation. Analog comparators with internal 6-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency.

The Analog Front End (AFE) contains up to seven comparators with up to three integrated DACs, one VREFOUT-buffered DAC, up to four PGAs, and up to four digital filters. The PGAs can amplify the input signal in three discrete gain modes. The actual number of AFE peripherals will depend upon the TMS320F2805x device number. See Device Comparison for more details.

To learn more about the C2000 MCUs, visit the C2000™ real-time control MCUs page.

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