Processor cores:
- Up to Four C7x floating point, vector DSP, up to 1.0GHz, 320GFLOPS, 1024GOPS
- Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32TOPS (8b) at 1.0GHz
- Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
- Depth and Motion Processing Accelerators (DMPAC)
- Eight Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
- 2MB shared L2 cache per quad-core Cortex-A72 cluster
- 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
- Eight Arm Cortex-R5F MCUs at up to 1.0GHz
- 32K I-Cache, 32K D-Cache, 64K L2 TCM
- Two Arm Cortex-R5F MCUs in isolated MCU subsystem
- Six Arm Cortex-R5F MCUs in general compute partition
- GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s
- Custom-designed interconnect fabric supporting near max processing entitlement
Memory subsystem:
- Up to 8MB of on-chip L3 RAM with ECC and coherency
- ECC error protection
- Shared coherent cache
- Supports internal DMA engine
- Up to Four External Memory Interface (EMIF) module with ECC
- Supports LPDDR4 memory types
- Supports speeds up to 4266MT/s
- Up to 4x32-b bus with inline ECC up to 68GB/s
- General-Purpose Memory Controller (GPMC)
- 3x512KB on-chip SRAM in MAIN domain, protected by ECC
Functional Safety:
- Functional Safety-Compliant (on select part numbers)
- Developed for functional safety applications
- Documentation available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL D/SIL 3
- Systematic capability up to ASIL D/SC 3
- Hardware integrity up to ASIL D/SIL 3 for MCU Domain
- Hardware integrity up to ASIL B/SIL 2 for Main Domain
- Hardware integrity up to ASIL D/SIL 3 for Extended MCU (EMCU) portion of the Main Domain
- Safety-related certification
- AEC-Q100 qualified on part number variants ending in Q1
Device security (on select part numbers):
- Secure boot with secure run-time support
- Customer programmable root key, up to RSA-4K or ECC-512
- Embedded hardware security module
- Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES
High speed serial interfaces:
- Integrated Ethernet switch supporting up to 8 (TDA4xH) or 4 (TDA4xP) external ports
- Two ports support 5Gb, 10Gb USXGMII/XFI
- All ports support 1Gb, 2.5Gb SGMII
- All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes
- Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP) PCI-Express (PCIe) Gen3 controllers
- Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
- One USB 3.0 dual-role device (DRD) subsystem
- Enhanced SuperSpeed Gen1 Port
- Supports Type-C switching
- Independently configurable as USB host, USB peripheral, or USB DRD
- Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
- MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
- CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
- CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
- ECC verification/correction with CRC check + ECC on RAM
- Virtual Channel support (up to 16)
- Ability to write stream data directly to DDR via DMA
Ethernet:
- Two RGMII/RMII interfaces
Automotive interfaces:
- Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support
Display subsystem:
- Two DSI 4L TX (up to 2.5k)
- One eDP/DP interface with Multi-Display Support (MST)
- One DPI
Audio interfaces:
- Five Multichannel Audio Serial Port (MCASP) modules
Video acceleration:
- H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH) or 480MP/s (TDA4xP)
Flash memory interfaces:
- Embedded MultiMediaCard Interface ( eMMC™ 5.1)
- One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
- Universal Flash Storage (UFS 2.1) interface with two lanes
- Two independent flash interfaces configured as
- One OSPI or HyperBus™ or QSPI flash interfaces, and
- One QSPI flash interface
System-on-Chip (SoC) architecture:
- 16-nm FinFET technology
- 31mm × 31mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing
TPS6594-Q1 Companion Power Management ICs (PMIC):
- Functional Safety-Compliant support up to ASIL D/SIL 3
- Flexible mapping to support different use cases
Processor cores:
- Up to Four C7x floating point, vector DSP, up to 1.0GHz, 320GFLOPS, 1024GOPS
- Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32TOPS (8b) at 1.0GHz
- Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
- Depth and Motion Processing Accelerators (DMPAC)
- Eight Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
- 2MB shared L2 cache per quad-core Cortex-A72 cluster
- 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
- Eight Arm Cortex-R5F MCUs at up to 1.0GHz
- 32K I-Cache, 32K D-Cache, 64K L2 TCM
- Two Arm Cortex-R5F MCUs in isolated MCU subsystem
- Six Arm Cortex-R5F MCUs in general compute partition
- GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s
- Custom-designed interconnect fabric supporting near max processing entitlement
Memory subsystem:
- Up to 8MB of on-chip L3 RAM with ECC and coherency
- ECC error protection
- Shared coherent cache
- Supports internal DMA engine
- Up to Four External Memory Interface (EMIF) module with ECC
- Supports LPDDR4 memory types
- Supports speeds up to 4266MT/s
- Up to 4x32-b bus with inline ECC up to 68GB/s
- General-Purpose Memory Controller (GPMC)
- 3x512KB on-chip SRAM in MAIN domain, protected by ECC
Functional Safety:
- Functional Safety-Compliant (on select part numbers)
- Developed for functional safety applications
- Documentation available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL D/SIL 3
- Systematic capability up to ASIL D/SC 3
- Hardware integrity up to ASIL D/SIL 3 for MCU Domain
- Hardware integrity up to ASIL B/SIL 2 for Main Domain
- Hardware integrity up to ASIL D/SIL 3 for Extended MCU (EMCU) portion of the Main Domain
- Safety-related certification
- AEC-Q100 qualified on part number variants ending in Q1
Device security (on select part numbers):
- Secure boot with secure run-time support
- Customer programmable root key, up to RSA-4K or ECC-512
- Embedded hardware security module
- Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES
High speed serial interfaces:
- Integrated Ethernet switch supporting up to 8 (TDA4xH) or 4 (TDA4xP) external ports
- Two ports support 5Gb, 10Gb USXGMII/XFI
- All ports support 1Gb, 2.5Gb SGMII
- All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes
- Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP) PCI-Express (PCIe) Gen3 controllers
- Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
- One USB 3.0 dual-role device (DRD) subsystem
- Enhanced SuperSpeed Gen1 Port
- Supports Type-C switching
- Independently configurable as USB host, USB peripheral, or USB DRD
- Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
- MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
- CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
- CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
- ECC verification/correction with CRC check + ECC on RAM
- Virtual Channel support (up to 16)
- Ability to write stream data directly to DDR via DMA
Ethernet:
- Two RGMII/RMII interfaces
Automotive interfaces:
- Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support
Display subsystem:
- Two DSI 4L TX (up to 2.5k)
- One eDP/DP interface with Multi-Display Support (MST)
- One DPI
Audio interfaces:
- Five Multichannel Audio Serial Port (MCASP) modules
Video acceleration:
- H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH) or 480MP/s (TDA4xP)
Flash memory interfaces:
- Embedded MultiMediaCard Interface ( eMMC™ 5.1)
- One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
- Universal Flash Storage (UFS 2.1) interface with two lanes
- Two independent flash interfaces configured as
- One OSPI or HyperBus™ or QSPI flash interfaces, and
- One QSPI flash interface
System-on-Chip (SoC) architecture:
- 16-nm FinFET technology
- 31mm × 31mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing
TPS6594-Q1 Companion Power Management ICs (PMIC):
- Functional Safety-Compliant support up to ASIL D/SIL 3
- Flexible mapping to support different use cases
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