Product
0
SN74LVC112A
  • SN74LVC112A
  • SN74LVC112A
  • SN74LVC112A
  • SN74LVC112A
  • SN74LVC112A

SN74LVC112A

ACTIVE

Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset

Texas Instruments SN74LVC112A Product Info

1 April 2026 2

Parameters

Number of channels

2

Technology family

LVC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

3.6

Input type

TTL/CMOS

Output type

Push-Pull

Clock frequency (MHz)

150

Supply current (max) (µA)

10

IOL (max) (mA)

24

IOH (max) (mA)

-24

Features

Balanced outputs, Clear, Negative edge triggered, Over-voltage tolerant inputs, Preset, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Package

SOIC (D)-16-59.4 mm² 9.9 x 6

Features

  • Operates from 1.65V to 3.6V
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.8ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250mA per JESD 17
  • Operates from 1.65V to 3.6V
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.8ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250mA per JESD 17

Description

This dual negative-edge-triggered J-K flip-flop is designed for 1.65V to 3.6V VCC operation.

This dual negative-edge-triggered J-K flip-flop is designed for 1.65V to 3.6V VCC operation.

Subscribe to Welllinkchips !
Your Name
* Email
Popular Posts
Featured Parts More >
Submit a request
CONTACT US
Company address

WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK

Send Enquiry
SEND e-MAIL
Office hour from 9am to 6pm ,
Monday through Friday, UTC/GMT +8