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SN74LV27A
  • SN74LV27A
  • SN74LV27A
  • SN74LV27A
  • SN74LV27A
  • SN74LV27A
  • SN74LV27A
  • SN74LV27A

SN74LV27A

ACTIVE

3-ch, 3-input, 2-V to 5.5-V NOR gates

Texas Instruments SN74LV27A Product Info

1 April 2026 0

Parameters

Technology family

LV-A

Number of channels

3

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Inputs per channel

3

IOL (max) (mA)

12

IOH (max) (mA)

-12

Output type

Push-Pull

Input type

Standard CMOS

Features

Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

70

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Package

SOIC (D)-14-51.9 mm² 8.65 x 6

Features

  • Operation of 2-V to 5.5-V V CC
  • Max t pd of 7 ns at 5 V
  • Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, TA = 25°C
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Operation of 2-V to 5.5-V V CC
  • Max t pd of 7 ns at 5 V
  • Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, TA = 25°C
  • I off Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Description

These triple 3-input positive-NOR gates are designed for 2-V to 5.5-V V CC operation.

The SN74LV27A devices perform the Boolean function Y = A + B + C in positive logic.

These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

These triple 3-input positive-NOR gates are designed for 2-V to 5.5-V V CC operation.

The SN74LV27A devices perform the Boolean function Y = A + B + C in positive logic.

These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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