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SN74HC573A
  • SN74HC573A
  • SN74HC573A
  • SN74HC573A
  • SN74HC573A

SN74HC573A

ACTIVE

Octal Transparent D-Type Latches With 3-State Outputs

Texas Instruments SN74HC573A Product Info

1 April 2026 1

Parameters

Number of channels

8

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

28

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

80

Features

Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Package

PDIP (N)-20-228.702 mm² 24.33 x 9.4

Features

  • Wide Operating Voltage Range from 2 V to 6 V
  • High-Current 3-State Outputs Drive Bus Lines Directly up to 15 LSTTL Loads
  • Low Power Consumption: 80-µA Maximum ICC
  • Typical tpd = 21 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current: 1 µA (Maximum)
  • Bus-Structured Pinout
  • Wide Operating Voltage Range from 2 V to 6 V
  • High-Current 3-State Outputs Drive Bus Lines Directly up to 15 LSTTL Loads
  • Low Power Consumption: 80-µA Maximum ICC
  • Typical tpd = 21 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current: 1 µA (Maximum)
  • Bus-Structured Pinout

Description

The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.

The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.

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