0
ACTIVE
Number of channels |
8 |
Technology family |
HC |
Supply voltage (min) (V) |
2 |
Supply voltage (max) (V) |
6 |
Input type |
Standard CMOS |
Output type |
Push-Pull |
Clock frequency (max) (MHz) |
28 |
IOL (max) (mA) |
5.2 |
IOH (max) (mA) |
-5.2 |
Supply current (max) (µA) |
80 |
Features |
Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
Operating temperature range (°C) |
-40 to 125 |
Rating |
Automotive |
SOIC (DW)-20-131.84 mm² 12.8 x 10.3
This circuit is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK
