Texas Instruments SN74AUP1G125 Product Info

Parameters

Technology family	AUP
Supply voltage (min) (V)	0.8
Supply voltage (max) (V)	3.6
Number of channels	1
IOL (max) (mA)	4
Supply current (max) (µA)	0.9
IOH (max) (mA)	-4
Input type	Standard CMOS
Output type	3-State
Features	Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)
Rating	Catalog
Operating temperature range (°C)	-40 to 85

Package

DSBGA (YFP)-6-1.4000000000000001 mm² 1 x 1.4000000000000001

Features

Available in the Texas Instruments NanoStar™ Package
Low Static-Power Consumption
(I_CC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(C_pd = 4 pF Typical at 3.3 V)
Low Input Capacitance (C_I = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot
< 10% of V_CC
Input-Disable Feature Allows Floating Input Conditions
I_off Supports Partial-Power-Down Mode Operation
Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
Wide Operating V_CC Range of 0.8 V to 3.6 V
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.6 ns Maximum at 3.3 V

Available in the Texas Instruments NanoStar™ Package
Low Static-Power Consumption
(I_CC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(C_pd = 4 pF Typical at 3.3 V)
Low Input Capacitance (C_I = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot
< 10% of V_CC
Input-Disable Feature Allows Floating Input Conditions
I_off Supports Partial-Power-Down Mode Operation
Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
Wide Operating V_CC Range of 0.8 V to 3.6 V
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.6 ns Maximum at 3.3 V

Description

The SN74AUP1G125 bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, OE must be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AUP1G125 bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, OE must be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ELECTRONIC COMPONENTS
All In One Distributor

SN74AUP1G125

Single 0.8-V to 3.6-V low power buffer with 3-state outputs

Texas Instruments SN74AUP1G125 Product Info

Parameters

Package

Features

Description

SUBMITTED SUCCESSFULLY！

ELECTRONIC COMPONENTS All In One Distributor

SN74AUP1G125

Single 0.8-V to 3.6-V low power buffer with 3-state outputs

Texas Instruments SN74AUP1G125 Product Info

Parameters

Package

Features

Description

SUBMITTED SUCCESSFULLY！

ELECTRONIC COMPONENTS
All In One Distributor