Texas Instruments SN74AUP1G02 Product Info

Parameters

Technology family	AUP
Number of channels	1
Supply voltage (min) (V)	0.8
Supply voltage (max) (V)	3.6
Inputs per channel	2
IOL (max) (mA)	4
IOH (max) (mA)	-4
Output type	Push-Pull
Input type	Standard CMOS
Features	Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)
Data rate (max) (Mbps)	100
Rating	Catalog
Operating temperature range (°C)	-40 to 85

DSBGA (YFP)-6-1.4000000000000001 mm² 1 x 1.4000000000000001

Available in the Ultra Small 0.64 mm² Package (DPW) with 0.5-mm Pitch
Low Static-Power Consumption
(I_CC = 0.9 µA Max)
Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typ at 3.3 V)
Low Input Capacitance (C_i = 1.5 pF Typ)
Low Noise – Overshoot and Undershoot
<10% of V_CC
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Input Hysteresis Allows Slow Input Transition and Better Switching-Noise Immunity at the Input
(V_hys = 250 mV Typ at 3.3 V)
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.6 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
  (A114-B, Class II)
- 1000-V Charged-Device Model (C101)

Available in the Ultra Small 0.64 mm² Package (DPW) with 0.5-mm Pitch
Low Static-Power Consumption
(I_CC = 0.9 µA Max)
Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typ at 3.3 V)
Low Input Capacitance (C_i = 1.5 pF Typ)
Low Noise – Overshoot and Undershoot
<10% of V_CC
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Input Hysteresis Allows Slow Input Transition and Better Switching-Noise Immunity at the Input
(V_hys = 250 mV Typ at 3.3 V)
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.6 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
  (A114-B, Class II)
- 1000-V Charged-Device Model (C101)

This single 2-input positive-NOR gate performs the Boolean function Y = A + B or Y = A × B in positive logic.