0
ACTIVE
Number of channels |
8 |
Technology family |
ALVC |
Supply voltage (min) (V) |
1.65 |
Supply voltage (max) (V) |
3.6 |
Input type |
Standard CMOS |
Output type |
3-State |
Clock frequency (max) (MHz) |
150 |
IOL (max) (mA) |
24 |
IOH (max) (mA) |
-24 |
Supply current (max) (µA) |
10 |
Features |
Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) |
Operating temperature range (°C) |
-40 to 85 |
Rating |
Catalog |
SOIC (DW)-20-131.84 mm² 12.8 x 10.3
This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK
