0
ACTIVE
Supply voltage (min) (V) |
1.65 |
Supply voltage (max) (V) |
3.6 |
Number of channels |
18 |
IOL (max) (mA) |
24 |
IOH (max) (mA) |
-32 |
Input type |
Standard CMOS |
Output type |
3-State |
Features |
Balanced outputs, Bus-hold, Positive input clamp diode, Ultra high speed (tpd <5ns) |
Technology family |
ALVC |
Rating |
Catalog |
Operating temperature range (°C) |
-40 to 85 |
TSSOP (DGG)-64-137.7 mm² 17 x 8.1
Widebus+ and UBT are trademarks of Texas Instruments Incorporated.
This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.
The SN74ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When SEL is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The A and B I/Os and APAR and BPAR inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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