0
ACTIVE
Configuration |
Universal |
Bits (#) |
8 |
Technology family |
FCT |
Supply voltage (min) (V) |
4.75 |
Supply voltage (max) (V) |
5.25 |
Input type |
Standard CMOS |
Output type |
3-State |
Clock frequency (MHz) |
70 |
IOL (max) (mA) |
64 |
IOH (max) (mA) |
-32 |
Supply current (max) (µA) |
200 |
Features |
High speed (tpd 10-50ns), Partial power down (Ioff) |
Operating temperature range (°C) |
-40 to 85 |
Rating |
Catalog |
SOIC (DW)-24-159.65 mm² 15.5 x 10.3
The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0 and S1).
The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.
In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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