0
ACTIVE
Bits (#) |
16 |
Data rate (max) (Mbps) |
300 |
Topology |
Push-Pull |
Direction control (typ) |
Direction-controlled |
Vin (min) (V) |
2.5 |
Vin (max) (V) |
3.3 |
Vout (min) (V) |
3.3 |
Vout (max) (V) |
5 |
Applications |
GPIO |
Features |
Output enable, Very high speed |
Technology family |
ALVC |
Supply current (max) (mA) |
0.04 |
Rating |
Catalog |
Operating temperature range (°C) |
-40 to 85 |
SSOP (DL)-48-164.358 mm² 15.88 x 10.35
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This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa.
The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA.
To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
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