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SN74AHC594-Q1
  • SN74AHC594-Q1
  • SN74AHC594-Q1
  • SN74AHC594-Q1
  • SN74AHC594-Q1

SN74AHC594-Q1

ACTIVE

Automotive 2V-to-5.5V 8-bit shift registers with output registers

Texas Instruments SN74AHC594-Q1 Product Info

1 April 2026 0

Parameters

Configuration

Serial-in

Bits (#)

8

Technology family

AHC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (MHz)

115

IOL (max) (mA)

8

IOH (max) (mA)

-8

Supply current (max) (µA)

40

Features

Balanced outputs, Output register, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Package

TSSOP (PW)-16-32 mm² 5 x 6.4

Features

  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN (WBQA) package
  • Operating range 2V to 5.5V VCC
  • Low delay, 12ns (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN (WBQA) package
  • Operating range 2V to 5.5V VCC
  • Low delay, 12ns (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17

Description

The SN74AHC594-Q1 is an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR, SRCLR) inputs are provided on both the shift and storage registers. A serial (QH’) output is provided for cascading purposes.

Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

The SN74AHC594-Q1 is an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR, SRCLR) inputs are provided on both the shift and storage registers. A serial (QH’) output is provided for cascading purposes.

Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

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