0
ACTIVE
Number of channels |
8 |
Technology family |
AHC |
Supply voltage (min) (V) |
2 |
Supply voltage (max) (V) |
5.5 |
Input type |
Standard CMOS |
Output type |
Push-Pull |
Clock frequency (max) (MHz) |
110 |
IOL (max) (mA) |
8 |
IOH (max) (mA) |
-8 |
Supply current (max) (µA) |
40 |
Features |
Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs |
Operating temperature range (°C) |
-40 to 125 |
Rating |
Catalog |
PDIP (N)-20-228.702 mm² 24.33 x 9.4
These devices are positive-edge-triggered D-type flip-flops with a direct clear ( CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
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